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Description
The AT43USB380 is a straightforward upgrade of the AT43USB370 Host/Function Processor to support the USB 2.0 On-The-Go (OTG) specification. It can operate either as a single-chip Host/Function Processor or if used in conjunction with an external Atmel Charge Pump, as a full OTG solution. The AT43USB380 is functionally equivalent to the AT43USB370 as a Host/Function Processor and can be used in place of the AT43USB370 in the existing AT43USB370 design with minor hardware modifications. The pinout differences between the AT43USB370 and the AT43USB380 are due to the inclusion of the on-chip OTG interface in the AT43USB380. To support OTG functionality, an external Charge Pump has to be connected to the OTG interface of the AT43USB380, as shown in Figure 1 on page 7. The external Charge Pump serves in the following two capacities: 1. As a power source to the downstream USB devices. 2. As a signaling interface during the OTG session negotiation upon connection. From the hardware standpoint, the AT43USB380 is equivalent to the AT43USB370 with the following exceptions: * On-chip OTG Interface. This hardware block is added to the AT43USB380 to support the OTG functionality. Signals in the OTG interface include ID, DISCHARGE, PUMP, CONTROL, EN, SESS_VLD, SESS_END, SESS_HIGH and SESS_LOW. This interface is used during an OTG session to determine the roles of the AT43USB380 and the connected OTG-enabled USB device either as a host or a function. 8/16/32 Bit Generic Host Processor Interface. The AT43USB380 has a variable width, generic host processor interface whereas the AT43USB370 supports only 32-bit host interface. The width of the host interface on the AT43USB380 is determined by firmware configuration. Simplified System Interface. The GPIOs required in AT43USB370 for handshaking are no longer required in AT43USB380. The system processor can write directly to the AT43USB380 registers thus eliminates the need for PROG, SEL, READY, DONE, MORE, INTR_IN signals. The WAIT_N signal is not needed either. It is only there for precaution for SYS_CLK synchronization. Up to 16 GPIO Pins. GPIO pins are multiplexed with the host processor interface. When the interface to the host processor is 8 or 16 bits, up to 16 of the unused pins in the host processor interface can be used as GPIO pins. High level APIs are provided to access these GPIO pins.
On-The-Go Upgrade of the AT43USB370 USB 2.0 Full-Speed Host/Function Processor AT43USB380 Upgrade Map Summary
*
*
*
From the standpoint of the firmware development environment, the AT43USB380 shares the same high level APIs and low level fir mware librar ies with the AT43USB370. Additions to the AT43USB380 firmware suite include: * * High level APIs specific to the OTG support. The number of additional APIs is less than 10. Low level OTG firmware embedded in the AT43USB380 hardware that support Host Negotiation Protocol (HNP) and Session Request Protocol (SRP).
The AT43USB380 share the same debugging tools with the AT43USB370 as well. During development, the AT43USB380 should be treated as a black box in terms of
3420AS-USB-03/04
Note: This is a summary document. A complete document is not available at this time. For more information, please contact your local Atmel sales office.
USB functionality. Communication with the AT43USB380 is achieved through a small set (less than 25) of high level, ANSI C-compliant APIs. The actual USB protocol including HNP and SRP is transparent to the host processor.
AT43USB380 OTG Processor Pin Description
Table 1 gives the description of the pins. Table 1. Pin Description of the AT43USB380
Signal Name System Interface Host system clock input for synchronization of WAIT_N and DREQ_N. (Synchronization requirement can be enable/disable through internal register settings) System Address Bus CHIP_SELECT signal from System (ARM(R)) System Data Bus [15:0] BWIDTH[1:0]=1x : System Data Bus [31:16] BWIDTH[1:0]=0x : GPIO[15:0] DMA Acknowledge from System (ARM) DMA Request to System (ARM) Interrupt to System (ARM) OUTPUT_ENABLE from System (ARM) WAIT to System (ARM) WRITE_ENABLE from System (ARM) System Data Bus Size: 00 : 8 Bit Interface D[7:0] 01 : 16 Bit Interface D[15:0] 1x : 32 Bit Interface D[31:0] Wakeup Request from System Dir. Polarity Width Description
SYS_CLK
I
1
A[7:0] CS_N D[15:0] D[31:16]/ GPIO[15:0] DACK_N DREQ_N INTR_OUT OE_N WAIT_N WE_N
I I B B I O O I O I LO LO HI LO LO LO LO
8 1 16 16 1 1 1 1 1 1
BWIDTH[1:0]
I
2
WAKEUP_N USB Interface DM DP ID RPU_EN RPD_EN
I
LO
1
B B I O O
1 1 1 1 1
USB Line (D-) USB Line (D+) OTG device type identification; used to differentiate a Mini-A and Mini-B plug Enable resistive pull-up to the D+ line Enable resistive pull-down to the D+/D- lines
Charge Pump Interface CPClk EN PUMP_EN O O O 1 1 1 Charge Pump clock output Charge Pump; Enable for Charge Pump Charge Pump; Enable for Charge Pump
2
AT43USB380 Upgrade Map Summary
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AT43USB380 Upgrade Map Summary
Table 1. Pin Description of the AT43USB380 (Continued)
Signal Name SESS_VLD SESS_END SESS_LOW SESS_HIGH Dir. I I I I Polarity Width 1 1 1 1 Description Charge Pump; Active high when VBUS > VSESS_VLD otherwise "0" Charge Pump; Active high when VBUS > VSESS_END otherwise "0" Charge Pump; Active high when VBUS > VSESS_LOW otherwise "0" Charge Pump; Active high when VBUS > VSESS_HIGH otherwise "0" Limits the current output of the Charge Pump. Used during VBUS pulsing when configured as B-device Charge Pump; Connect VBUS to ground
LOW_CUR DISCHARGE Oscillator, Clocks XTAL1 XTAL2 LFT CLK_SEL RESET_N Jtag Interface TCK/SI
O O
1 1
I O I I I LO
1 1 1 1 1
Oscillator input Oscillator output PLL loop filter Clock Source selection between crystal and external oscillator RESET for USB Processor
I
1
TP3=0: JTAG Clock - from JTAG controller; TP3=1: SI-EEPROM TP3=0: JTAG Serial Data IN - from JTAG controller; TP3=1: SCK-EEPROM TP3=0: JTAG Serial Data OUT - from JTAG controller; TP3=1: SO-EEPROM TP3=0: JTAG Mode Select - from JTAG controller; TP3=1: CS-EEPROM JTAG Reset - from JTAG controller
TDI/SCK
I
1
TDO/SO
O
1
TMS/CS TRST_N Test Pins TP0 TP1 TP2 TP3 TP4/SCAN_EN TP_CLK /D_CLK TP_RCV_DATA /RCV_DATA
I I LO
1 1
I I I I I O O
1 1 1 1 1 1 1
Test pin 0 Test Pin 1 Test pin 2 Test pin 3 Test pin 4/SCAN_EN Clock test output/SIE DPLL extracted clock Extracted serial data test output
3
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Table 1. Pin Description of the AT43USB380 (Continued)
Signal Name Dir. Polarity Width Description
Power/Ground Pins VEXT18 VDD VSS O I 3 5 10 1.8V regulated output 3.3V input Ground
AT43USB380 OTG Processor Pin Assignment
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Signal A7 A6 A5 A4 A3 A2 A1 A0 CS_N OE_N WE_N INTR_OUT VSS VDD18 VDD SYS_CLK WAIT_N DREQ_N DACK_N CPClk DISCHARGE EN LOW_CUR PUMP_EN SESS_LOW VSS SESS_VLD SESS_HIGH SESS_END Type Input Input Input Input Input Input Input Input Input Input Input Output Power Supply/Ground Power Supply/Ground Power Supply/Ground Input Output Output Input Output Output Output Output Output Input Power Supply/Ground Input Input Input
4
AT43USB380 Upgrade Map Summary
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AT43USB380 Upgrade Map Summary
Pin # 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 Signal ID TP0 TP1 CLK_SEL VSS XTAL1 XTAL2 LFT VDD18 VDD VSS DM DP TP2 TP3 RPD_EN RPU_EN RESET_N TCK/SI TMS/CS VDD VSS TDI/SCK TDO/SO TRST_N TP_CLK/D_CLK TP_RCV_DATA/RCV_DATA TP4/scan_en BWIDTH[0] WAKEUP_N D31/GPIO[15] D30/GPIO[14] D29/GPIO[13] D28/GPIO[12] VSS VDD18 VDD Type Input Input Input Input Power Supply/Ground Input Output Input Power Supply/Ground Power Supply/Ground Power Supply/Ground Bi-directional Bi-directional Input Input Output Output Input Input Input Power Supply/Ground Power Supply/Ground Input Output Input Output Output Input Input Input Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Ground Power Supply/Ground Power Supply/Ground
5
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Pin # 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Signal D27/GPIO[11] D26/GPIO]10] D25/GPIO[9] D24/GPIO[8] D23/GPIO[7] D22/GPIO[6] D21/GPIO[5] D20/GPIO[4] VDD VSS D19/GPIO[3] D18/GPIO[2] D17/GPIO[1] D16/GPIO[0] BWIDTH[1] D15 D14 D13 D12 D11 VDD VSS D10 D9 D8 D7 D6 D5 VSS D4 D3 D2 D1 D0
Type Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Ground Power Supply/Ground Bi-directional Bi-directional Bi-directional Bi-directional Input Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Ground Power Supply/Ground Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Power Supply/Ground Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional
6
AT43USB380 Upgrade Map Summary
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AT43USB380 Upgrade Map Summary
USB-OTG Interface Connections for Host Mode
Figure 1. AT43USB380 USB and Charge Pump Connection for Host Mode
3.3V DP 100 kOhm ID DP DM 15 kOhm RPD_EN 15 kOhm DM
Mini-AB Receptacle
ID VBUS GND
AT43USB380 (OTG Interface)
DISCHARGE PUMP_EN LOW_CUR EN CPCLK SESS_VLD SESS_END SESS_HIGH SESS_LOW 3.3V
Charge Pump AT43CD001
DISCHARGE PUMP_EN LOW_CUR EN CLK SESS_VLD SESS_END SESS_HIGH SESS_LOW VSSAC VBUS C2 C1 VDDAC DP DM 3.3V
B Receptacle
VBUS GND
CEXT1 10 kOhm SELECT CEXT2 C3
7
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3420AS-USB-03/04

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